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Realization of Fast-Operating System for Synchronization of Frequency with Fractional Divider

Abstract

The paper considers one variant for increasing fast-operation of a frequency synthesizer with a small step of an output grid that is a realization of an equivalent fractional division factor with the help of a digital counter synthesizer (DCS). Analysis of static synthesizer parameters has been executed at a number of DCS controlling variants.

References

1. Разработка методов построения и анализ источников колебаний дискретного множества частот: отчет № 3. – Т. II. Инв. номер Б864907. - Минск, 1979.

2. Синтезатор с дробно-рациональной аппроксимацией произвольных значений частоты / В. В. Бодряков [и др.] // Стабилизация частоты : материалы межотраслевых науч.-техн. конф., совещаний, семинаров и выставок. – М. : ВИМИ, 1978.

3. Frequency synthesis: Techniques and application / Edited by J. Gorsky-Popiel. – IEEE PRESS, 1975. – P. 174.


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Kuznetsov A.P., Markov A.V., Alqatawneh H.A. Realization of Fast-Operating System for Synchronization of Frequency with Fractional Divider. ENERGETIKA. Proceedings of CIS higher education institutions and power engineering associations. 2007;(5):48-61. (In Russ.)

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ISSN 1029-7448 (Print)
ISSN 2414-0341 (Online)